The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them.
The design-cycle of VLSI-chips consists of different consecutive steps from high-level synthesis (functional design) to production (packaging). The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them. The main concern in the physical design of VLSI-chips is to find a layout with minimal area, further the total wirelength has to be minimized. For some critical nets there are hard limitations for the maximal wirelength.
The physical architecture is the physical layout of a system and its components in a schema. It refers to some representation of the structure or organization of the physical elements of the system. The physical architecture should be part of the Allocated and Product Baselines.
This classical approach of the physical design is strongly serial with many interdependencies between the sub-steps. For example during floorplanning and global routing there must be enough routing space reserved to complete the exact wiring in the detailed routing phase. Otherwise the placement has to be corrected and the global routing has to be computed again.
Primary Responsibilities and Requirements.
BE/B.Tech/ME/M.Tech 3 years to 15 years.
- He/She should be able to do top-level floor planning, PG Planning, Partitioning, Placement, Scan-Chain-Reordering,Clock Tree Synthesis,Timing Optimization, SI aware routing,Timing Analysis/closure and ECO tasks(timing and functional ECOs),SI closure, design rule checks(DRC),logical vs. Schematic(LVS) checks,Antenna checks. HE/She should have worked on 65nm or lower node designs with adv power techniques such as Voltage Islands, Power Gating and substrate-bias
- Provide technical guidance, mentoring to physical design engrs.
- Interface with front-end ASIC teams to resolve issues.
- Low Power Design-Voltage Islands, Power Gating, Substrate-bias techniques.
- Timing closure on DDR2/DDR3/PCIE interfaces.
- Excellent communication skills.
- Strong Background of ASIC Physical Design:Floor planning, P&R,extraction, IR Drop Analysis, Timing AND Signal Integrity closure.
- Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
- Expertise in scripting languages such as PERL, TCL.
- Strong Physical Verification skill set.
- Static Timing Analysis in Primetime or Primetime-SI.
- Good written and oral communication skills. Ability to clearly document plans.
- Ability to interface with different teams and prioritize work based on project needs.
